120 wafers/hour. Zero inspection bottleneck.
The parallel inference pipeline processes each die frame in under 8ms. Even at 300mm wafer sizes with 1000+ die per wafer, inspection never holds the line.
How parallelism prevents wait states
The inspection pipeline separates sensor capture, frame queuing, inference, and result dispatch into independent stages. Each stage runs concurrently — the sensor never waits for inference to finish.
Optical sensor captures die image frames at trigger intervals. Frame metadata (wafer ID, die X/Y, recipe ID) appended at capture time.
Frames normalized and batched (batch size 16). Queue depth stays below 5% fill at rated throughput — burst capacity up to 200 frames.
Batched frames distributed across GPU workers. Each worker processes one batch independently. Results returned to ordered result buffer.
Defect classifications committed to local database and pushed via SECS/GEM S6F11 events. Full wafer map available at lot completion.
Multi-GPU configurations
The standard unit ships with a two-GPU configuration rated for 120 wafers/hour. For higher-throughput fabs or 12-inch wafers with high die count, a three-GPU variant supports up to 160 wafers/hour.
Throughput numbers are measured at standard 300mm fab conditions with 1024-die wafer density. Actual throughput varies with die size, optical step count, and tool configuration.
| Config | GPUs | Max wph | Die/hr |
|---|---|---|---|
| Standard | 2× | 120 | 122,880 |
| Extended | 3× | 160 | 163,840 |
| Evaluation | 1× | 70 | 71,680 |
*At 1024 die/wafer, 300mm standard. Measured values, not projections.
Verify throughput on your process configuration
Share your wafer spec, die count, and inspection step count — we'll provide a throughput projection specific to your configuration before evaluation.