Engineering documentation for your evaluation
White papers, application notes, and integration checklists for process engineers, quality teams, and fab integration engineers.
Technical depth for evaluation teams
False-Positive Rate Methodology in Automated Wafer Inspection
46 pages. Covers adaptive threshold calibration algorithm, per-recipe validation protocol, and benchmark comparison against static threshold systems and human inspectors. Includes 7nm, 5nm, and 28nm case data.
View White PaperThird-Shift Inspection Parity: Quantifying Human Inspector Performance Degradation
31 pages. Statistical analysis of defect escape rates across three shifts at a 300mm logic facility. Methodology for establishing machine inspection baseline equivalence to first-shift human performance.
View White PaperImplementation guidance
SECS/GEM Integration Checklist for 300mm Fab Environments
18 pages. Step-by-step host communication configuration, ATC qualification procedure, event subscription setup, and MES push verification. Covers HSMS-SS and SECS-II RS-232 transport.
View Application NoteRecipe Qualification Protocol for 7nm Logic Gate Layers
22 pages. Detailed qualification procedure for 7nm logic inspection recipes. Covers calibration wafer selection, initial threshold configuration, false-positive review workflow, and production sign-off criteria.
View Application NoteIntegrating Lenspathio Defect Maps with APC / SPC Systems
14 pages. Data export format specification, SPC chart integration, and correlation of inspection defect density with downstream electrical test yield.
View Application NoteEdge Chip Detection at the 300mm Wafer Perimeter
11 pages. Configuration guide for edge-specific inspection algorithms. Covers notch region handling, exclusion zone setup, and edge chip confidence threshold tuning.
View Application NoteRequest the full documentation package
Evaluation teams receive the complete technical package including all white papers, application notes, and SEMI compliance documentation.