White Paper — WP-001
46 pages
False-Positive Rate Methodology in Automated Wafer Inspection
Detailed treatment of per-recipe adaptive threshold calibration. Covers the calibration algorithm, convergence behavior (lots 1–50, 51–200, 200+), drift correction mechanisms, and benchmark comparison against static threshold systems. Includes false-positive data from 7nm logic, 5nm logic, and 28nm DRAM process nodes. Provides validation protocol for process engineers transitioning from human-assisted inspection.
White Paper — WP-002
31 pages
Third-Shift Inspection Parity: Quantifying Human Inspector Performance Degradation
Statistical analysis of defect escape rates across three shifts at a 300mm logic facility over a 6-month period. Quantifies first-to-third-shift detection rate degradation by defect class (particles, scratches, edge chips). Establishes methodology for demonstrating machine inspection equivalence to first-shift baseline in process qualification documentation.
White Paper — WP-003
28 pages
CNN Architecture for Semiconductor Defect Classification at 7nm and Below
Technical overview of the convolutional neural network architecture used in Lenspathio's base detection model. Describes training data composition, defect library curation, feature extraction layer design, and per-class precision/recall performance. Includes resolution analysis comparing 7nm versus 28nm input requirements.