Gate-All-Around Transistors and the Inspection Challenges No One Is Talking About
11 min read
Engineering Blog
Engineering notes on wafer inspection and yield.
Process node challenges, SECS/GEM protocol details, CNN classifier methodology, and defect taxonomy analysis. Written by process and ML engineers for readers who know what a KLARF file is.
Setting Confidence Thresholds for Human Review Escalation: A Framework for QA Engineers
7 min read
GaN and SiC Defect Modes: Adapting Optical Inspection for Compound Semiconductor Production
9 min read
Inspection as a Throughput Bottleneck: Data from 12 Months of Production Line Measurement
8 min read
Defect Detection at 5nm and 3nm: Early Results from Emerging Node Production Lines
10 min read
EMI Hardening Vision Systems for the Fab Floor: Specifications That Actually Matter
9 min read
KLARF Output Format and the Automated Review Workflow: What Every Process Engineer Should Know
8 min read
3D NAND vs Logic: Why Memory and Logic Fabs Need Different Inspection Strategies
7 min read
Training CNNs on Synthetic Wafer Images: Addressing the Labeled Data Shortage in Semiconductor Inspection
11 min read
On-Premises Deployment for Inspection Software: Protecting Fab IP in a Cloud-First World
6 min read
Defect Classification at 7nm: Why Optical Resolution Alone Is Not Enough
9 min read
Integrating Computer Vision Systems with SECS/GEM: A Practical Guide for Process Engineers
10 min read
The Hidden Cost of False Positives: How a 2% FPR Erodes Fab Yield Economics
8 min read
Why Third-Shift Fatigue Causes 60% of Escaped Defects in Wafer Visual Inspection
7 min read