Technology / Node Coverage
Process node coverage — 28nm to 3nm
Six process nodes, five defect categories. Validated detection coverage across the logic and memory manufacturing roadmap.
Coverage Matrix
Detection capability by node and defect type
Full circle = validated detection. Half circle = partial support (limited defect subtypes). Empty circle = roadmap item.
Node Details
What changes at each node transition
28nm → 16nm: FinFET introduction
FinFET transition introduces new defect modes: fin collapse, fin height non-uniformity, and mandrel etch residues. Pattern defect detection adds FinFET-specific reference die comparison logic at 16nm.
16nm → 7nm: EUV preparation
Single-exposure EUV begins at some 7nm implementations. Stochastic defect modes (EUV-specific bridge and void defects) require dedicated training data at 7nm — these don't appear at 16nm or 10nm.
7nm → 5nm: Particle sensitivity
At 5nm, particle size that causes a print defect is smaller than 10nm. Detection sensitivity below 20nm particle size requires 193nm illumination wavelength — the system switches automatically for 5nm lots.
5nm → 3nm: GAA transistors
Gate-All-Around nanosheet transistors at 3nm have new defect signatures: nanosheet uniformity, inner spacer void formation, and nanosheet separation. The v2.1 module adds dedicated GAA defect classifiers.
What process node is your evaluation?
Our evaluation program is configured to your specific process node. Tell us your node, device type, and process step of interest — we'll run the full pipeline on your wafer data.