Solutions / Memory
Memory device inspection for 3D NAND and DRAM
Stacking layer defect detection, bit-cell uniformity maps, and high-aspect-ratio etch monitoring — for memory fab process engineers.
Memory-Specific Inspection
3D NAND and DRAM defect detection
Memory fabs face defect modes that don't exist in logic manufacturing. High-aspect-ratio etch, stacked layer uniformity, and bit-cell pattern regularity all require dedicated inspection approaches.
3D NAND stacking layer defects
Layer-to-layer registration in 128L+ NAND stacks, etch stop layer discontinuities, and channel hole uniformity. Optical darkfield mode detects stacking defects not visible in standard brightfield inspection.
Bit-cell uniformity mapping
Statistical mapping of bit-cell electrical uniformity across the 300mm wafer. Regions of non-uniform cell sizing correlate with threshold voltage distribution variance — caught before electrical test.
HAR etch monitoring
High-aspect-ratio etch into 3D NAND stacks can produce bowing, twisting, and incomplete etch-through. Optical signature changes at the film stack surface are detectable before destructive cross-section analysis.
DRAM capacitor defects
Capacitor cell height non-uniformity and collapsed storage node pillars in DRAM are inspectable at the post-etch step. High-density defect mapping at 300mm scale identifies systematic process variation before film deposition.
Integration
Built for memory fab infrastructure
High-throughput lot inspection
Memory fabs run high-volume lots. 120 wph on 300mm wafers ensures inspection doesn't become the throughput bottleneck, even at volume production cycle times.
Yield correlation reports
Inspection defect maps correlate with downstream electrical test yield at die level. Systematic defect signatures appear as spatial patterns in the yield map before electrical test wafers are available.
MES-driven lot disposition
Wafer-level pass/fail decisions output to MES in real time via SECS/GEM. Lot hold triggers configurable by defect density threshold, critical defect count, or confidence score threshold — no manual disposition step required.
Memory fab evaluation program.
Run the evaluation on your 3D NAND or DRAM wafers. We configure the inspection parameters for your stack geometry and process step of interest. Results delivered with full wafer map and defect taxonomy breakdown.