Solutions
Logic, memory, and compound semiconductor — separate classifier models, same platform.
GaN epitaxial surface textures and silicon bridge defects require entirely different training data. Lenspathio maintains dedicated optical calibration and classifier training sets per device type — not a one-recipe-fits-all configuration.
Logic Devices
FinFET and Gate-All-Around at 5nm/3nm. Targeted detection of bridge defects, OPC errors, and overlay shift. Configured for logic foundry QA engineers who need sub-0.1% FPR at advanced nodes.
Logic solutionMemory Devices
3D NAND and DRAM inspection. Stacking layer defect detection and bit-cell uniformity mapping. Optimized for memory fab process engineers managing high-aspect-ratio etch and deposition yield.
Memory solutionCompound Semiconductor
GaN and SiC power devices. Epitaxial layer defect detection, substrate bow detection, and hexagonal crystal defect identification. For power semiconductor manufacturers at volume production.
Compound solutionShared Capabilities
Consistent foundation across device types
Sub-0.1% FPR across all device types
The false positive rate specification holds across silicon, compound semiconductor, and memory device wafers. Each device type has dedicated training data and optical calibration parameters.
SECS/GEM integration for all environments
Same integration architecture regardless of device type. Logic foundries, memory fabs, and power semiconductor lines all use the same SECS/GEM II and GEM 300 protocol stack.
Evaluation-first for every engagement
Every device type starts with a structured evaluation on your actual wafer data. No process-node-specific assumptions in the evaluation scope — your data, your device, your conditions.
On-premises deployment everywhere
Whether you're a logic foundry with strict IP requirements or a power semiconductor manufacturer with legacy infrastructure — on-premises deployment with air-gap compatibility is the same baseline for all customers.
Which device type is your evaluation?
Tell us your device type, process node, and inspection goals. We'll configure the evaluation around your specific wafer and defect profile.