GaN-on-SiC power devices and SiC MOSFETs are now in volume production for EV drivetrain inverters, solar inverters, and industrial motor drives. The fabs processing these materials are discovering that inspection tools and methods developed for silicon present systematic gaps when applied to wide-bandgap semiconductor production. The optical properties, crystallographic defect modes, and process characteristics of GaN and SiC require specific inspection adaptations that are not simply parameter changes on an existing silicon-tuned recipe.
Material Optical Properties and Their Inspection Implications
SiC has a bandgap of approximately 3.2 eV (4H-SiC), which means it is transparent at visible wavelengths and absorbs UV below approximately 390 nm. GaN has a bandgap of approximately 3.4 eV and is similarly transparent in visible wavelengths, absorbing below approximately 365 nm. This transparency has two consequences for optical inspection.
First, broadband brightfield inspection using illumination in the visible range (400–700 nm) does not interact with the SiC or GaN crystal in the same way it interacts with silicon. Silicon at visible wavelengths has a relatively high absorption coefficient — light does not penetrate deeply into the substrate, and surface topology changes produce strong reflectance contrasts. In SiC and GaN at visible wavelengths, the absorption length is much greater, meaning illumination penetrates into the substrate, interacts with subsurface structures, and creates reflectance patterns that are not purely surface-topology-determined. An inspection algorithm calibrated on silicon surface response behavior will misinterpret these subsurface interactions as surface anomalies.
Second, the UV wavelengths that do interact strongly with SiC and GaN surfaces (below 365 nm) are outside the spectral range of many broadband inspection systems that were designed for silicon. Inspection systems operating below 360 nm wavelength are available but are less common in fabs transitioning from silicon to wide-bandgap devices. Fabs procuring inspection capability for GaN or SiC production should explicitly specify UV wavelength capability as a requirement, not assume that a silicon-optimized brightfield system will perform equivalently.
Crystallographic Defects Specific to SiC and GaN
The defect taxonomy for SiC and GaN production includes crystallographic defect types not found in silicon that have direct device performance and reliability impact.
In SiC, the most consequential crystallographic defect for device yield is the micropipe — a hollow core threading dislocation that propagates through the full wafer thickness. Micropipes are characterized by their optical signature in UV-illuminated brightfield: they appear as dark spots with a characteristic size in the range of 1–50 µm depending on the dislocation Burgers vector magnitude. Micropipe density in commercial 4H-SiC substrates has improved substantially over the past decade (from tens per cm² to sub-0.1 per cm² in premium production-grade material), but individual micropipes remain yield killers for high-voltage devices because they cause local breakdown at fields well below the theoretical SiC limit.
Threading screw dislocations (TSDs) and threading edge dislocations (TEDs) in SiC and GaN, while not as catastrophically yield-limiting as micropipes, affect device performance by acting as recombination centers and preferential sites for forward bias degradation in bipolar devices. These dislocations are not visually distinguishable by standard optical inspection; their detection requires synchrotron X-ray topography or etch pit density (EPD) measurements that reveal the dislocation emergence points at the surface.
In GaN epitaxial layers grown on SiC or sapphire substrates, V-pit defects — inverted pyramid-shaped openings in the GaN surface formed at threading dislocation sites — are a characteristic surface defect. V-pits are optically visible in brightfield as dark, roughly hexagonal features with sizes in the range of 50–500 nm, depending on the GaN growth conditions. Their density correlates with the threading dislocation density in the underlying substrate and is a process control metric for MOCVD growth optimization.
Surface Roughness and Its Effect on Inspection Sensitivity
SiC substrates — particularly after CMP to device-quality surface finish — have a much lower surface roughness (Ra < 0.3 nm) than silicon substrates at equivalent process stage, because SiC polishing chemistry has matured to deliver extremely flat surfaces. This low roughness is a sensitivity advantage for optical inspection: a smoother background surface produces less background scatter, improving signal-to-noise for small particulate detection.
However, SiC substrates are significantly harder than silicon (Mohs hardness ~9.2 vs ~7 for silicon) and require much higher polishing forces and longer polishing times. The polishing process introduces a characteristic scratch population that is specific to SiC CMP: long, low-angle scratches from abrasive particles dragged across the hard SiC surface. These scratches are typically 50–200 nm deep and several hundred microns to millimeter scale in length. They appear as bright linear features in darkfield inspection and as faint contrast-modulated lines in brightfield. Their optical signature differs from the scratch morphology seen in silicon after CMP, and classifiers trained on silicon scratch signatures may not correctly classify SiC CMP scratches without specific SiC training data.
We are not saying that silicon inspection classifiers are completely incompatible with SiC applications — some defect types (particles, edge chips, handling damage) have similar optical signatures across substrate materials. The point is that material-specific defect types (CMP scratch morphology, crystallographic defect features, surface micro-steps from crystal cutting) require targeted classifier training on SiC-specific image data, not assumed coverage from silicon-trained models.
GaN-on-SiC Epitaxial Layer Inspection
The most inspection-intensive steps in GaN power device production are at the epitaxial layer. MOCVD growth of the AlGaN/GaN heterostructure for HEMT devices introduces several defect modes: hillocks (growth mounds at screw dislocation emergence sites), pits (V-pits at threading dislocations as described above), surface morphology variations from temperature or precursor flow non-uniformity across the wafer, and particulate incorporation from the reactor chamber walls.
Hillock defects in GaN present an inspection challenge because they have a characteristic pyramidal morphology with faceted side walls. Under brightfield illumination, the facet angle creates a characteristic star-shaped reflection pattern that can be mistaken for a particle by classifiers not trained on GaN-specific morphology. Darkfield inspection at oblique incidence angles, which preferentially scatters from sloped surfaces, generates a different signature for hillocks than for particles and enables more reliable discrimination when the inspection system supports multiple illumination angles.
Epitaxial wafer inspection also needs to contend with the periodic surface morphology from step-flow growth, which produces a surface with a regular atomic-scale terrace structure. At the magnifications used for macro-scale defect detection (low to medium NA), this terrace structure is not resolved. At higher NA used for fine-feature inspection, the terrace structure may generate periodic optical contrast that background-subtraction algorithms must handle correctly to avoid false detections from the normal surface morphology.
Inspection Step Placement for Wide-Bandgap Production
An inspection strategy for GaN or SiC device production should include: incoming substrate qualification (micropipe density, surface roughness, polytype verification for SiC), post-epitaxial growth inspection (hillock and pit density, surface morphology uniformity), and post-MESA etch inspection (edge profile quality, sidewall roughness). These are the steps most directly correlated with device performance in the wide-bandgap device failure mode taxonomy.
Many GaN and SiC device fabs are adapted from III-V or silicon facilities and are deploying inspection capability incrementally as volume ramps. The incoming substrate qualification step is the highest-leverage starting point because substrate defect density directly propagates into device yield and because substrate cost for SiC is still substantially higher than silicon, making incoming quality screening economically significant per wafer.