Gate-all-around (GAA) nanosheet transistors represent the most significant FEOL structural change in a generation. The transition from FinFETs — which have been in production since ~22nm — to GAA nanosheets at the 2nm node and below is not just a scaling step. It is an architectural change that introduces process steps, material stacks, and defect mechanisms that the inspection community is still learning to address.
Most discussions of GAA focus on device performance: improved electrostatic control, better short-channel behavior, stackable nanosheet count for drive current optimization. The inspection implications have received far less attention, despite the fact that GAA process flows contain several new high-criticality inspection challenges that existing FinFET-era approaches do not adequately cover.
What GAA Changes Structurally
In a FinFET, the gate electrode wraps around three sides of a silicon fin (top and two sidewalls). The channel is the fin body; the fin geometry is defined by a relatively straightforward etch process followed by a conformal high-k/metal gate (HKMG) deposition. Inspection at FinFET process steps has been well-characterized over many production generations.
In a GAA nanosheet transistor, multiple horizontally stacked silicon nanosheets (typically 3–5 per stack) serve as the channel. The gate wraps completely around each nanosheet — all four sides, hence "gate-all-around." This requires a process sequence that does not exist in FinFET flows: selective etch of the SiGe sacrificial layers between the Si nanosheets (the "sheet release" step) using a chemistry that etches SiGe while leaving Si substantially intact. This selective etch must achieve complete removal of the SiGe without damaging the Si nanosheet surfaces, without collapsing the nanosheet stack structure, and without leaving SiGe residue that would prevent gate dielectric conformality on the nanosheet undersides.
The sheet release step is an inspection problem that does not exist in FinFET processes. There is no post-FinFET equivalent — nothing in FinFET production involves etching away a sacrificial material sandwiched between the active device regions. It is a genuinely new process step with genuinely new failure modes, and the inspection approaches to characterize it are still being developed alongside the process itself.
The Nanosheet Inspection Problem
Nanosheets at 2nm nodes are 5–7 nm thick. Their lateral dimensions (width per nanosheet) depend on device design but are in the range of 15–30 nm for logic applications and can be narrower for SRAM. These are structures that are invisible to broadband optical inspection not because the resolution is insufficient to detect a single nanosheet, but because the optical interaction with a 6 nm silicon slab embedded in a stack of dielectric and metal materials produces a diffracted optical signature that is dominated by the surrounding materials, not the nanosheet itself.
What optical inspection can detect at GAA process steps: systematic yield-relevant events at scales larger than the nanosheet features — particles on the surface, residue contamination from SiGe etch that covers multiple nanosheet stacks, local etch non-uniformity visible as a reflectance change over an area spanning multiple die, and structural collapse events that produce topographic changes visible at macro scale. What optical inspection cannot directly detect: incomplete sheet release affecting individual nanosheet gaps, thickness non-uniformity within individual nanosheets, interface quality between the gate dielectric and nanosheet surface, or SiGe residue at the atomic scale.
This creates a coverage gap at the most critical process step in GAA production. The sheet release etch is where incomplete removal directly causes gate-dielectric non-conformality and threshold voltage non-uniformity — but the optical inspection system deployed at the step provides limited direct sensitivity to the failure modes that matter most for transistor performance.
Inner Spacer Formation and Its Failure Modes
Inner spacers — the dielectric plugs that separate the gate metal from the source/drain epitaxy at the lateral edges of each nanosheet — are a GAA-specific structure with no FinFET equivalent. They are formed by: first recessing the SiGe sacrificial layer laterally at each stack level to create a cavity, then depositing a low-k dielectric to fill the cavity and form the spacer, then etching back the dielectric to expose the Si nanosheet sidewalls for source/drain epitaxy.
Inner spacer uniformity — consistent recess depth, consistent fill, consistent etch-back — across all nanosheet levels in a stack is a yield-critical requirement. Non-uniformity in inner spacer dimensions causes NMOS-to-PMOS imbalance, threshold voltage variation, and in severe cases, parasitic gate-to-source/drain capacitance that degrades performance.
Optical inspection sensitivity to inner spacer formation is indirect at best. Inner spacer dimensions are inside the nanosheet stack — they are sub-surface features in a structure with feature sizes well below optical resolution. What inspection can observe are proxy signals: changes in the surface optical signature that correlate with inner spacer process excursions at wafer-map scale, which requires careful baseline characterization to distinguish from normal process variation. Process teams working on GAA inner spacer characterization are increasingly reliant on cross-section TEM (transmission electron microscopy) and XPS (X-ray photoelectron spectroscopy) for direct inner spacer metrology, with optical inspection providing process stability monitoring rather than direct defect detection.
Gate Metal Fill in Wrapped Geometries
In FinFET, the gate metal fills a relatively simple trench geometry — the gate wraps around the fin top and sides, and metal fill (typically tungsten or cobalt) fills from the top. In GAA, the gate metal must fill completely around each nanosheet, including the underside of each sheet in a multi-nanosheet stack. The narrowest gap in this fill geometry — the space between adjacent nanosheets filled by gate metal — can be as small as 7–10 nm. Complete fill of these narrow inter-nanosheet gaps, without voiding, is a process window challenge that does not have a direct FinFET analog.
Gate metal voids in the inter-nanosheet gap do not have an optical inspection signature — they are sub-resolution, sub-surface, and buried within the gate electrode after metal fill. Their yield impact (local gate resistance increase, non-uniform electrostatic control, reliability risk from metal migration at high field) manifests at electrical test. By the time electrical test detects a voiding-related yield problem, the wafers have already been through the entire downstream BEOL process flow — a substantial invested cost.
The inspection approach that has the most sensitivity to gate metal voids at GAA nodes is electrical test structure characterization: specifically, gate resistance test structures with narrow inter-electrode separations matching the nanosheet gap dimensions, measured at wafer sort before die cut. This places the detection point after the full process flow but before final packaging, enabling a rework decision or at minimum preventing bad die from reaching assembly.
Where Optical Inspection Remains High-Value in GAA Flows
We are not arguing that optical inspection loses its utility for GAA production — quite the opposite. The inspection challenges above are concentrated in specific FEOL process steps involving sub-resolution structures. The majority of GAA process steps, particularly the EUV lithography patterning steps, BEOL metallization, and mid-of-line contact formation, benefit from optical inspection in the same way that FinFET production does.
Particle contamination control — ensuring that particles do not land on the nanosheet stack surface before sheet release, which would shadow the etch and cause incomplete release — is a high-leverage optical inspection application specific to GAA. A particle on the surface before sheet release that causes a local incomplete release can fail a transistor (or multiple transistors if the particle is large) in a way that is difficult to detect optically after the fact but that could have been caught by inspection before the etch step. Pre-sheet-release inspection for particles therefore has a prevention value that post-process inspection cannot achieve.
EUV stochastic defect monitoring at the nanosheet patterning steps is another high-value application. The narrow nanosheet widths in GAA designs are patterned at pitches at the aggressive end of EUV capability, and stochastic resist failures (missing nanosheets, deformed nanosheets from edge roughness variation) are yield-relevant at these pitches. The monitoring approach is the same as described for 5nm/3nm production: optical screening for macroscopic events, electrical test structures for stochastic sensitivity, combined to give a complete picture.
The Inspection Coverage Map GAA Teams Need
Process teams qualifying GAA production should develop an explicit inspection coverage map that identifies — for each process step — the yield-relevant failure modes, the inspection method that provides sensitivity to each failure mode, and the detection limit of each method relative to the smallest failure mode dimension that causes yield impact. This coverage map will necessarily include gaps: process steps where the critical failure modes are below any optical detection limit and must be monitored through electrical test structures, cross-section metrology sampling, or inline metrology (scatterometry, optical CD) rather than inspection.
Understanding where the gaps are is as important as deploying the inspection steps that do provide coverage. A coverage map with explicitly identified gaps enables a deliberate risk management conversation — which gaps are acceptable because alternative monitoring provides equivalent protection, and which gaps represent genuine blind spots that increase yield risk without compensating monitoring. GAA production teams that treat their optical inspection plan as comprehensive coverage, without a gap analysis, will consistently be surprised by yield failures at process steps that the inspection architecture did not actually cover.
The sheet release step and inner spacer formation are the two process steps where this conversation is most urgent. Both are new to GAA, both have critical failure modes below optical resolution, and both are early in the device build where catching failures early would prevent substantial downstream process investment. The metrology tools that can directly characterize these steps — TEM, SAXS for nanosheet stack characterization, electrical inline test — should be part of the process control plan from first-silicon qualification, not added in response to yield problems after production has started.