ML architecture purpose-built for cleanroom conditions
Convolutional inference designed for fab-floor electromagnetic interference, ambient vibration, and resist chemistry variation. Not adapted from general-purpose computer vision — built specifically for semiconductor defect classification.
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Four design principles
Semiconductor-specific training data
Models trained on semiconductor defect image libraries — not general object detection adapted from ImageNet. Training includes controlled samples of each defect class at multiple process nodes and from multiple tool types.
Per-recipe adaptive calibration
Each recipe (process node + layer + tool) gets its own threshold profile derived from the first 50 production wafers. The calibration layer adjusts automatically as process conditions evolve. Keeps false-positive rates stable across tool lifetimes.
On-premises inference, no cloud
All ML inference runs on the local industrial compute unit. No wafer image data leaves your facility. No network dependency for inspection uptime. IP protection built into the deployment model.
EMI-hardened capture pipeline
Frame capture and pre-processing pipeline designed for fab-floor electromagnetic interference conditions. Optical sensor timing and capture sequencing validated against SEMI S22 equipment installation standards.
Model + calibration layer separation
The base CNN model handles feature extraction — it learns what semiconductor defects look like in general. The per-recipe calibration layer handles the specific characteristics of your tool and process: optical aberrations, resist reflectance variation, background texture.
This separation means the base model can be updated (improved defect coverage, finer resolution) without invalidating your accumulated recipe calibrations — critical in production environments where re-qualification is expensive.
False-Positive Control Deep DiveGo deeper
False-Positive Control Methodology
How per-recipe adaptive calibration keeps false-positive rates below 0.1% across tool lifetimes, process chemistry variation, and ambient cleanroom conditions.
Read methodology White PaperFalse-Positive Rate Methodology in Automated Wafer Inspection
46-page engineering report with methodology detail, benchmark data, and validation protocols for process engineers and quality teams.
Download white paperRequest a technical briefing
45-minute technical walkthrough with our engineering team. Covers model architecture, calibration methodology, and integration requirements specific to your process configuration.